In the semiconductor art, it is desirable to improve transistor performance even as devices become smaller due to ongoing scaling. Reduced device scaling with conventional gate dielectrics creates problems in manufacturing reliable MOS transistors, including short channel effects (SCE). It is known in the prior art to use high-k dielectric materials as the gate dielectric material to improve device performance. For purposes of this description, a high-k dielectric is a material having a dielectric constant k greater than that of silicon dioxide, the traditional dielectric material, which has a dielectric constant of approximately 3.9. Materials with a dielectric constant of greater than 3.9 are said to be “high-k” dielectrics. High-k dielectrics provide a similar equivalent oxide thickness (EOT) to larger scaled devices while using a reduced actual dielectric thickness, which meets the reduced scaling requirements of advanced CMOS processes. The use of such materials creates additional problems, however, in the manufacturing and reliability of the transistor devices, including a threshold voltage (Vt) variability in the MOS transistors, particularly of p-type MOS transistors, which makes commercial devices using the high-k dielectric materials less desirable. Further, reduction in scale and the use of certain desirable high-k dielectric materials on silicon substrates is believed to contribute to a reported degradation in carrier mobility, which has a negative effect on the performance of transistors manufactured using these materials.
A paper entitled “A Highly Manufacturable Low Power and High Speed HfSiO CMOS FET with Dual Poly-Si Gate Electrodes,” by Iwamoto et al., International Electronics Devices Meeting of the IEEE (IEDM), December 2003, describes a MOSFET of the p-type which uses a particular high-k gate dielectric material, HfSiO, over a silicon substrate, and describes the use of certain sidewalls and a channel controlling step to improve the Vt variability effects. This paper describes the threshold voltage shift problem particularly observed in p-type MOS transistors that are fabricated using high-k dielectric materials.
A paper entitled “Fermi Level Pinning at the PolySi/Metal Oxide Interface”, by Hobbs et al., 2003 Symposium on VLSI Technology Digest of Technical Papers, describes the role of the poly Si/metal oxide interface on threshold voltage and how it influences poly Si depletion.
A paper entitled “55 nm High Mobility SiGE(:C) pMOSFETS with HfO2 Gate Dielectric and TiN Metal Gate for Advanced CMOS,” by Weber et al., 2004 Symposium on VLSI Technology, Digest of Technical Papers, describes the improved transistor performance obtained for a pMOS transistor fabricated using a SiGe channel material grown by epitaxial deposition of a compressively strained SiGe layer, with a high-k gate dielectric of HfO2, and a metal gate electrode of TiN, having improved carrier mobility and improved Vt.
A paper entitled “Mobility Enhancement in Surface Channel SiGe PMOSFETs with HfO2 Gate Dielectrics”, by Shi et al., IEEE Electron Device Letters, Vol. 24, No. 1, January 2003, describes PMOS transistors fabricated using strained SiGe as the channel layer and HfO2 as the dielectric, the paper describes enhanced mobility for the devices over conventional silicon devices but also describes a variance in the threshold voltages.
A paper entitled “<100> Strained SiGe Channel p MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance”, by Shima, Fujitsu Science and Technology Journal 39, Vol. 1, pp. 78-83 (June 2003), describes results obtained in carrier mobility experiments with strained SiGe as a channel material in PMOS devices.
The need for a process and apparatus for a producible, enhanced performance, scalable MOS transistor with a high-k gate dielectric thus exists. These needs are addressed in the present invention.